cross pond high tech

RISC-V is having itself a moment.

What began as an effort to produce an open-source ISA for low-end microcontrollers and other simple kinds of chips is becoming a genuine ecosystem. RISC-V CPUs still can’t challenge the likes of a Cortex-A76 or x86 CPU, but they’re creeping up the performance charts. Two recent developments could give the project a further boost: First, MIPS (formerly Wave Computing) has announced it will begin developing its own RISC-V CPUs. Second, China’s new Loongson CPU, based on the MIPS64 architecture, may be looking for a new ISA.

Wave Computing was an AI company developing around a MIPS architecture that eventually bought MIPS Technologies itself before collapsing into bankruptcy. In the aftermath, Wave announced it would rebrand as MIPS. Back in the 1980s and early 1990s, MIPS Technologies (not just MIPS) was a RISC CPU developer who found success in the 1980s before being acquired by SGI in the early 1990s. SGI eventually decided to go with the then-upcoming Itanium in lieu of continuing to develop its own in-house CPUs, so MIPS was reborn as a tech licensing company.

MIPS enjoyed a bit of a run very early in the history of Android, but ARM’s growing hegemony drove it from the marketplace. Since then, we haven’t heard much about the ISA. It’s a little odd for Wave Computing to rebrand as MIPS, then declare it was building a new RISC-V CPU, but that’s what the company has done.

“Going forward, the restructured business will be known as MIPS, reflecting the company’s strategic focus on the groundbreaking RISC-based processor architectures which were originally developed by MIPS,” a company statement read. “MIPS is developing a new industry-leading standards-based 8th generation architecture, which will be based on the open-source RISC-V processor standard.”

As for the Loongson, we’ve talked about this CPU family before. Loongson is one of China’s homegrown CPU efforts and is built around MIPS64. The current iteration of the core is known as the Loongson 3B4000 and is reportedly clocked between 1.8GHz – 2GHz. It offers four cores and is built on a 28nm process. It’s said to offer a 128KB L1 split into 64KB L1i and 64KB L1d, and 256KB of L2 cache per core. There’s an 8MB L3 presumably shared between all cores.

The next iteration of the Loongson 5000 series, set to launch this year, will be the last variant of the CPU family to support the MIPS64 architecture. The Loongson 3A5000 is a quad-core chip for client PCs and the Loongson 3C5000 features up to 16 cores and is intended for servers. Both are expected to be fabbed at TSMC on a 12nm process node. THG reports that the chips are based on an internal architecture that’s fully MIPS64 compatible, with larger caches and a new memory controller.

Loongson’s executives have stated they are “looking forward to join the open-source instruction consortium,” which is being interpreted to mean that China intends to shift to RISC-V in the future.

The timing of these announcements probably isn’t coincidental. CIP United, a Chinese company, controls all MIPS licensing rights in China, Hong Kong, and Macau. It takes a few years to design a new CPU, which is why the Loongson project isn’t moving to RISC-V right away. If the Loongson 5000 family launches in 2021, we could reasonably expect to see the RISC-V-based follow-up in 2023 – 2024.

We’re still a few years away from RISC-V CPUs that can stand up to ARM or x86 cores, performance-wise, but there’s been a lot of interesting activity in this space the past few years. China is said to be ramping its efforts to create a semiconductor ecosystem that doesn’t depend on the United States. The country may feel that the open-source nature of the RISC-V ISA offers it the best chance to develop a CPU core that can’t be interdicted.

Xiaomi’s Mi Mix series has always pushed the boundaries of phone screens and form factors, from the original model that kicked off the bezel wars to last year’s sliding, notchless Mi Mix 3. Now, just as we’re starting to see “waterfall” displays with extreme curved edges, Xiaomi is taking this to a wild new level with the Mi Mix Alpha.

The “surround screen” on the Alpha wraps entirely around the device to the point where it meets the camera module on the other side. The effect is of a phone that’s almost completely made of screen, with status icons like network signal and battery charge level displayed on the side. Pressure-sensitive volume buttons are also shown on the side of the phone. Xiaomi is claiming more than 180 percent screen-to-body ratio, a stat that no longer makes any sense to cite at all.

The Mix Alpha uses Samsung’s new 108-megapixel camera sensor, which was co-developed with Xiaomi. As with other recent high-resolution Samsung sensors, pixels are combined into 2x2 squares for better light sensitivity in low light, which in this case will produce 27-megapixel images.

We’ll have to see how that works in practice, but the 1/1.33-inch sensor is unusually large for a phone and should give the Mix Alpha a lot of light-gathering capability. There’s also no need for a selfie camera — you just turn the phone around and use the rear portion of the display as a viewfinder for the 108-megapixel shooter.

On January 20-22 2018, around 1000 innovators converged to the City of Munich for the 14th time to mingle and listen to an impressive lineup of speakers : entrepreneurs, scientists, media experts, politicians and artists.

This year's theme was "reconquer" : here are my highlights.
The most impressive talks in my personal view were Lilium, AI & Robotics, with a specific mention to Scott Galloway's now famous yearly slideshow.

While you wait for the complete set of videos that will show up on DLD YouTube channel , please enjoy these short videos and slide shots assembled on a famous German band's song.