FPGA Implementation
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Where Does RTL lint tool fit in my design flow?

Where Does RTL lint tool fit in my design flow? | FPGA Implementation | Scoop.it
Working with ASIC and particularly FPGA designers, I’m frequently asked if finding bugs using existing simulation or emulation tools is sufficient. The short answer is “Yes”,but it’s not always the most efficient. As design sizes increase but schedules do not expand to match, designers find themselves frustrated by spending too much time looking at simulation …
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FPGA tools for more predictive needs in critical - Blue Pearl Software Inc.

FPGA tools for more predictive needs in critical - Blue Pearl Software Inc. | FPGA Implementation | Scoop.it
“Find bugs earlier.” Every software developer has heard that mantra. In many ways, SoC and FPGA design has become very similar to software development – but in a few crucial ways, it is very different. Those differences raise a new question we should be asking about uncovering defects: earlier than when? Structured development methodology was …
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Tcl scripts and managing messages in ASIC & FPGA debug 

Tcl scripts and managing messages in ASIC & FPGA debug  | FPGA Implementation | Scoop.it
Our previous Blue Pearl post looked at the breadth of contextual visualization capability in the GUI to speed up debug. Two other important aspects of the ASIC & FPGA pre-synthesis workflow are automating analysis with scripts and managing the stream of messages produced. Let’s look at these aspects in the latest Blue Pearl 2016.1 release. …
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Blue Pearl Visual Verification Suite automates design checking to improve design quality - Blue Pearl Software Inc.

Blue Pearl Visual Verification Suite automates design checking to improve design quality - Blue Pearl Software Inc. | FPGA Implementation | Scoop.it
Over the last couple of weeks, we have examined how we can debug our designs using Micrium’s ?C/Probe (Post 1 and Post 2) or with the JTAG to AXI Bridge. However, the best way to minimize time spent debugging is to generate high quality designs in the first place. We can then focus on ensuring that the design …
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Debugging Environment - Blue Pearl Software

Debugging Environment - Blue Pearl Software | FPGA Implementation | Scoop.it
Overview Only designers who make no mistakes can avoid debugging. The question is, how fast can you debug? That depends largely on how clearly the issues identified by your tools are presented. A good debugging environment can save hours of frustration and tedium. To quickly find pre-simulation and synthesis problems in chip designs, designer use …
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Automatic SDC Generation

Automatic SDC Generation | FPGA Implementation | Scoop.it
Blue Pearl’s SDC will automatically find the timing exceptions, that is, the false paths and multi cycle paths, and provide that information to the implementation tools
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Management Dashboard - Blue Pearl Software Inc.

Management Dashboard - Blue Pearl Software Inc. | FPGA Implementation | Scoop.it
Overview Guarantee high reliability RTL with the Visual Verification Suite Management Dashboard.The Blue Pearl Management Dashboard delivers real-time visibility to ASIC, FPGA and IP RTL design rule and CDC checks to better assess schedules, risk and overall design quality. This standalone option to the Visual Verification Suite, provides RTL Designers, Verification Engineers and Managers visual …
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Blue Pearl Verification Methodology Guide

The Blue Pearl Software Verification Methodology is a set of best practices and recommendations intended to streamline verification and signoff of IP, FPGA and ASIC RTL. The methodology is intended to be used in conjunction with the Visual Verification Suite in order to reduce design risk and to accelerate development.
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RTL Analysis for Complex FPGA designs using a Grey Cell Methodology to Improve QoR

The first issue has to do with sheer design size and the associated data volume. As designs go through several iterations before they stabilize, it is inefficient to be dragging along every piece of design information all the time.
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RTL Analysis – Systems Development Life Cycle ,Design a Program & Compliance

RTL Analysis – Systems Development Life Cycle ,Design a Program & Compliance | FPGA Implementation | Scoop.it
RTL Analysis provides unique combination of powerful built-in checks and formal analysis that gives comprehensive and powerful static design includes designing a computer programs, compliance & Systems Development Life Cycle to increase productivity.
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RTL Analysis for Complex FPGA designs using a Grey Cell Methodology to Improve QoR

As designs are getting more complex, we are seeing two major issues that customers have to deal with in the RTL analysis space.
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DVCon United States

DVCon United States | FPGA Implementation | Scoop.it
Topic: “Just Do It. Users Want Results, not Technology. Who Cares if a Structural Analysis Tools is Using Formal Verification?”
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Cross-viewing improves ASIC & FPGA debug efficiency - Blue Pearl Software Inc.

Cross-viewing improves ASIC & FPGA debug efficiency - Blue Pearl Software Inc. | FPGA Implementation | Scoop.it
We introduced the philosophy behind the Blue Pearl Software suite of tools for front-end analysis of ASIC & FPGA designs in a recent post. As we said in that discussion, effective automation helps find and remedy issues as each re-synthesis potentially turns up new defects. Why do Blue Pearl users say their tool suite is …
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The Value of High Reliability RTL for FPGA Design

The Value of High Reliability RTL for FPGA Design | FPGA Implementation | Scoop.it
John Molyneux, COO & Senior VP Sales and Marketing, Blue Pearl Software Introduction Today’s FPGA designs are typically developed by assembling between 50 to 100 unique IP blocks to form a complete System on Chip (SoC) including embedded processors, high speed serial interfaces, analog, signal processing and control logic. These systems are large, complex and …
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Medical Device Development and Testing

Medical Device Development and Testing | FPGA Implementation | Scoop.it
Medical Device Development and Testing Medical device safety and effectiveness plays a critical role in healthcare. The development, delivery, management and use of safe and effective medical devices, instrumentation and related technologies are critical to patient outcomes and healthcare worker safety. For medical device design teams, the creation of highly reliable and safe designs using …
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Advanced Technologies for IP and FPGA Verification

Advanced Technologies for IP and FPGA Verification | FPGA Implementation | Scoop.it
Renowned & Reliable EDA Software Company offers unique & powerful designing computer & circuit programs, mobile phones programs, designing rules from our engineering design program experts in California.
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Blue Pearl Software’s CDC Analysis Just Got a Whole Lot Faster

Blue Pearl Software’s CDC Analysis Just Got a Whole Lot Faster | FPGA Implementation | Scoop.it
Announcing Visual Verification Suite 2017.3 SANTA CLARA, California – Nov 8, 2017 – Blue Pearl Software, Inc., the leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced immediate availability of the Visual Verification Suite 2017.3. The Visual Verification Suite provides an advanced integrated RTL debugging, constraint generation and clock …
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Clock Domain Crossing ( CDC ) - Blue Pearl Software Inc

Clock Domain Crossing ( CDC ) - Blue Pearl Software Inc | FPGA Implementation | Scoop.it
The Blue Pearl Software Suite offers the capability to analyze designs for Clock Domain Crossing (CDC) issues
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What Makes a Great Verification Methodology - Blue Pearl Software Inc.

What Makes a Great Verification Methodology - Blue Pearl Software Inc. | FPGA Implementation | Scoop.it
Today’s modern Electronic Design Automation (EDA) tools are built to solve the most challenging of design problems. For IP, FPGA and ASIC design, most tools are developed leveraging modern software development methodologies such as Agile software design. Many also implement their software using languages that foster code reuse such as OOAD. EDA vendors, including Blue …
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Blue Pearl Software Unveils JumpStart Training and Consulting

Blue Pearl Software Unveils JumpStart Training and Consulting | FPGA Implementation | Scoop.it
Personalized JumpStart Services Ensure Out-of-the Box Productivity for ASIC, FPGA and IP RTL Verification SANTA CLARA, California – January 24, 2017 – Blue Pearl Software, Inc., a leading provider of Electronic Design Automation (EDA) software for ASIC, FPGA and IP design verification, today announced JumpStart training and consulting services. The JumpStart solution is included with …
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Blue Pearl Software Streamlines RTL Verification for Xilinx All Programmable FPGAs and SoCs - Blue Pearl Software Inc.

Visual Verification Suite 2017.2 Delivers Xilinx Tcl App for Vivado Design Suite Accelerating RTL Verification SANTA CLARA, California – July 25, 2017 – Blue Pearl Software, Inc., the leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced Visual Verification Suite 2017.2. The release extends Blue Pearl’s leadership in RTL …
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Accelerating Xilinx All Programmable FPGA and SoC Design Verification with Blue Pearl Software

Xilinx All Programmable FPGAs and SoCs are used across multiple markets, powering applications such as machine learning, embedded vision, industrial IoT to cloud computing. With devices approaching
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