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It looks like we finally have a launch date for Microsoft Office 2013: January 29th. The date comes courtesy of a pre-order page on Canadian retailer Future Shop's website for Microsoft's Office...
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Do you have a backup plan for your treasured photos?
Just imagine all the thousands of photos stored in phones, digital cameras and laptops. But what happens when you want to upgrade them, or heaven forbid, your device is lost or stolen?
Another great article from The *Official AndreasCY* ~ http://mcaf.ee/2b5x3
INBOUND 2013 presentation by Mike Volpe. Register for INBOUND 2014 at www.inbound.com
A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals. Of course, quality of an IP inside and outside of an SoC must be tested thoroughly. Considering today’s large SoC designs with multiple IPs, it’s imperative that effective debugging tools with easy and quick visualization, navigation, annotations etc. are a must for designers to make right decisions during the course of design. The designers should be able to easily analyze different parts of the design which can be in different languages such as Spice, Verilog, VHDL, SystemVerilog etc. and can have different levels of voltages and signals.Last week I attended a webinar (http://www.semiwiki.com/cgi-bin/clickthru.pl?http://www.edadirect.com/page.php?s=e) on Mixed Signal SoC Verification hosted by EDA Direct (http://www.semiwiki.com/cgi-bin/clickthru.pl?http://www.edadirect.com/) where they showcased StarVisionTM tool from Concept Engineering (http://www.semiwiki.com/cgi-bin/clickthru.pl?http://www.concept.de/)
SlideShare is the world’s largest community for sharing presentations. Discover great content and connect with like-minded individuals.
CoinDesk analyses key cryptocurrency trends, challenges, opportunities, and the outlook for Bitcoin in 2014 in its first Bitcoin report. Full PDF download is...
Framebench is a cloud based communication and feedback platform specially for digital agencies and creative design firms. Its your central workplace where you can store & share your creative assets.
The first precious seconds someone spends on your landing page determine the success or failure of your online campaign. Learn how to identify the Seven Dead...
In previous design generations interconnect could safely be modeled by extraction using just R and C values. Parasitics in interconnect are important because they can affect the operating frequency or phase error in circuits like VCO’s. The need to model parasitics properly in wires is just as applicable in PA’s, LNA’s and for clock lines, or any other place there is critical interconnect in high speed analog or RF circuits.Several things have changed that are now compelling designers to look more closely at interconnect parasitics. Up until now inductance was something that could be ignored. But with higher frequencies, even simple wires inside circuits are starting to look like transmission lines. The rule of thumb has been that when the length of the signal path was long enough to become some percentage of a wavelength that the line itself starts to become a concern for signal integrity. The question is
10345Actually these days even Baskin-Robbins has more, but not 505. But as it says in the title, Atmel have 505 different microcontrollers. That's a lot. Some are AVR, both 8 bit and 32 bit, and some are various flavors of ARM (all 32 bit) ranging from older parts like the ARM9 to various flavors of Cortex ranging from the M0 (tiny microcontroller with no pipeline or cache) up to A5. Of course the ARM product line goes all the way up to 64-bit Cortex-A57 and so on but they are not in any sense of the word microcontrollers and are really only used in SoCs and not standalone products.But with 505 choices, how do you pick one. It turns out that Atmel have made it relatively easy for you. They have a microcontroller product finder that allows you to put in your hard constraints and it will narrow down the
I have often written in Semiwiki about high speed PHY IP supporting Interface protocols (see for example this blog (https://www.semiwiki.com/forum/content/2787-phy-ip-supporting-mobile-application-tsmc-20nm.html)), the SoC cornerstone, almost as crucial as CPU, GPU or SDRAM Memory Controller. When you architect a SoC, you first select CPU(s) and/or GPU(s) to support the system basic functionality (Processor for Mobile application, Networking, Set-Top-Box etc.), then you define the various protocols to be supported by this SoC to interface with the functional system and the outside world. For an enterprise system, you will have to select one or several protocols among Ethernet (10G KR & KR4, 40G or 100G), PCI Express 3.0/2.1/1.1, SATA 6G/3G/1.5G or OIF CEI-6G and CEI-11G, to name a few. If you have read this previous blog (https://www.semiwiki.com/forum/content.php?r=2168-Rare-earth-syndrome-PHY-IP-analogy) (or if you have been exposed to high speed PHY utilization), you know that a 12 Gbps PHY IP design is complex, resource intensive and time consuming,
10356Last month India Electronics & Semiconductor Association (IESA (http://www.semiwiki.com/cgi-bin/clickthru.pl?http://www.iesaonline.org/)) held its Vision Summit at Bangalore in which luminaries from across the semiconductor and electronics industry presented their views about the future of this industry and India’s progress. Dr. Walden C. Rhines, Chairman and CEO of Mentor Graphics (http://www.semiwiki.com/cgi-bin/clickthru.pl?http://www.mentor.com/embedded-software/events/embedded-world) presented interesting facts and trends about the semiconductor industry in his keynote speech. Dr. Rhines, a great technologist, strategist and visionary, I admire, particularly talked about what makes India best suited to embrace the fabless opportunity in the overall semiconductor ecosystem. I’m moved by his insight into Indian semiconductor business dynamics, strengths, weaknesses and how he rightfully cites a sustainable opportunity for India to focus upon. So what are the trends? Which segment is gaining traction?10357If we look at the semiconductor market, fabless semiconductor design segment is showing the highest growth rate (16% CAGR), 29% of total IC revenue at $78B in
Last week I attended the SPIE Advanced Technology Conference. There were a lot of interesting papers and as is always the case at these conferences, there was a lot of interesting things to learn from talking to other attendees on the conference floor.The first interesting information from the conference floor was that 450mm is being pushed out. What I heard is that with low fab utilization and the empty fab 42 shell, Intel has pulled all of their resources off of 450mm. Intel was one of the key players pushing 450mm and the comments I heard were 450mm won’t be this decade with 2023 as the new introduction date for high volume manufacturing. Some equipment companies appear to be putting 450mm equipment development on hold.I think it is fair to say the conference was generally negative on EUV:TSMC presented a paper where they really called out ASML. TSMC showed a
US Navy destroyer, the USS Truxtun, has crossed Turkey's Bosphorus and entered the Black Sea. With the Crimea Peninsula getting ready to hold a referendum on independence from Ukraine in a week, the US is ramping up its military presence in the region.
OK, enough with octa-core mobile monstrosities for now. Let’s shift gears to Embedded World 2014 and the lower end of the spectrum, one that will make up the vast majority of devices on the Internet of Things: tiny, low power microcontrollers with integrated wireless connectivity. There still seems to be some stigma about putting RF into designs, and some of it is justified. One of our readers commented this week that Apple “does not have the know-how” in reference to integrated baseband LTE. On the contrary, I’d say: Apple can buy any IP or talent they want. Their reluctance stems more from the realities of supply chains and multiple carrier qualifications facing different requirements in worldwide markets, not a technology issue per se. RF designs still need proper care and feeding and regulatory clearance. We continue to see strides in RF integration – with attention now turning to