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Do you have a backup plan for your treasured photos?
Just imagine all the thousands of photos stored in phones, digital cameras and laptops. But what happens when you want to upgrade them, or heaven forbid, your device is lost or stolen?
Another great article from The *Official AndreasCY* ~ http://mcaf.ee/2b5x3
Professor Mark Z. Jacobson of the civil and environmental engineering department at Stanford University has been developing an environmental model...
A new multi-band satellite antenna developed by Imec in collaboration with Septentrio was announced at the Mobile World Conference held recently in...
Having talked previously about the broad range of connectors available, here we look at connectors that fight against that trend. We look at one such product, the Cloudsplitter from TE Connectivity.
INBOUND 2013 presentation by Mike Volpe. Register for INBOUND 2014 at www.inbound.com
A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals. Of course, quality of an IP inside and outside of an SoC must be tested thoroughly. Considering today’s large SoC designs with multiple IPs, it’s imperative that effective debugging tools with easy and quick visualization, navigation, annotations etc. are a must for designers to make right decisions during the course of design. The designers should be able to easily analyze different parts of the design which can be in different languages such as Spice, Verilog, VHDL, SystemVerilog etc. and can have different levels of voltages and signals.Last week I attended a webinar (http://www.semiwiki.com/cgi-bin/clickthru.pl?http://www.edadirect.com/page.php?s=e) on Mixed Signal SoC Verification hosted by EDA Direct (http://www.semiwiki.com/cgi-bin/clickthru.pl?http://www.edadirect.com/) where they showcased StarVisionTM tool from Concept Engineering (http://www.semiwiki.com/cgi-bin/clickthru.pl?http://www.concept.de/)
SlideShare is the world’s largest community for sharing presentations. Discover great content and connect with like-minded individuals.
CoinDesk analyses key cryptocurrency trends, challenges, opportunities, and the outlook for Bitcoin in 2014 in its first Bitcoin report. Full PDF download is...
Framebench is a cloud based communication and feedback platform specially for digital agencies and creative design firms. Its your central workplace where you can store & share your creative assets.
The first precious seconds someone spends on your landing page determine the success or failure of your online campaign. Learn how to identify the Seven Dead...
In previous design generations interconnect could safely be modeled by extraction using just R and C values. Parasitics in interconnect are important because they can affect the operating frequency or phase error in circuits like VCO’s. The need to model parasitics properly in wires is just as applicable in PA’s, LNA’s and for clock lines, or any other place there is critical interconnect in high speed analog or RF circuits.Several things have changed that are now compelling designers to look more closely at interconnect parasitics. Up until now inductance was something that could be ignored. But with higher frequencies, even simple wires inside circuits are starting to look like transmission lines. The rule of thumb has been that when the length of the signal path was long enough to become some percentage of a wavelength that the line itself starts to become a concern for signal integrity. The question is
10345Actually these days even Baskin-Robbins has more, but not 505. But as it says in the title, Atmel have 505 different microcontrollers. That's a lot. Some are AVR, both 8 bit and 32 bit, and some are various flavors of ARM (all 32 bit) ranging from older parts like the ARM9 to various flavors of Cortex ranging from the M0 (tiny microcontroller with no pipeline or cache) up to A5. Of course the ARM product line goes all the way up to 64-bit Cortex-A57 and so on but they are not in any sense of the word microcontrollers and are really only used in SoCs and not standalone products.But with 505 choices, how do you pick one. It turns out that Atmel have made it relatively easy for you. They have a microcontroller product finder that allows you to put in your hard constraints and it will narrow down the
I have often written in Semiwiki about high speed PHY IP supporting Interface protocols (see for example this blog (https://www.semiwiki.com/forum/content/2787-phy-ip-supporting-mobile-application-tsmc-20nm.html)), the SoC cornerstone, almost as crucial as CPU, GPU or SDRAM Memory Controller. When you architect a SoC, you first select CPU(s) and/or GPU(s) to support the system basic functionality (Processor for Mobile application, Networking, Set-Top-Box etc.), then you define the various protocols to be supported by this SoC to interface with the functional system and the outside world. For an enterprise system, you will have to select one or several protocols among Ethernet (10G KR & KR4, 40G or 100G), PCI Express 3.0/2.1/1.1, SATA 6G/3G/1.5G or OIF CEI-6G and CEI-11G, to name a few. If you have read this previous blog (https://www.semiwiki.com/forum/content.php?r=2168-Rare-earth-syndrome-PHY-IP-analogy) (or if you have been exposed to high speed PHY utilization), you know that a 12 Gbps PHY IP design is complex, resource intensive and time consuming,
Plotclock is something of a novelty, guaranteed to put a smile on your face. It uses an Arduino uno to control three R/C servos which guide a white...