UC Santa Barbara researchers have demonstrated a seamless design of an atomically-thin circuit with transistors and interconnects etched onto a seemingly impossible single layer of graphene.
The demonstration offers possibilities for ultra energy-efficient, flexible, and transparent electronics. Bulk materials commonly used to make CMOS transitors and interconnects pose fundamental challenges in continuous shrinking of their feature-sizes and suffer from increasing "contact resistance" between them, both of which lead to degrading performance and rising energy consumption.
"In addition to its atomically thin and pristine surfaces, graphene has a tunable band gap, which can be adjusted by lithographic sketching of patterns - narrow graphene ribbons can be made semiconducting while wider ribbons are metallic. Hence, contiguous graphene ribbons can be envisioned from the same starting material to design both active and passive devices in a seamless fashion and lower interface/contact resistances," explained Kaustav Banerjee, professor of electrical and computer engineering and director of the Nanoelectronics Research Lab at UCSB. Banerjee's research team also includes UCSB researchers Jiahao Kang, Deblina Sarkar and Yasin Khatami.
"Accurate evaluation of electrical transport through the various graphene nanoribbon based devices and interconnects and across their interfaces was key to our successful circuit design and optimization," explained Jiahao Kang, a PhD student in Banerjee's group and a co-author of the study. Banerjee's group pioneered a methodology using the Non-Equilibrium Green's Function (NEGF) technique to evaluate the performance of such complex circuit schemes involving many heterojunctions. This methodology was used in designing an "all-graphene" logic circuit reported in this study.
Via Dr. Stefan Gruenwald