The gate bias stress effects of multilayered MoS2 field effect transistors (FETs) with a back-gated configuration is investigated. The electrical stability of the MoS2 FETs can be significantly influenced by the electrical stress type, relative sweep rate, and stress time in an ambient environment. Specifically, when a positive gate bias stress was applied to the MoS2 FET, the current of the device decreased and its threshold shifted in the positive gate bias direction. In contrast, with a negative gate bias stress, the current of the device increased and the threshold shifted in the negative gate bias direction. The gate bias stress effects were enhanced when a gate bias was applied for a longer time or when a slower sweep rate was used. These phenomena can be explained by the charge trapping due to the adsorption or desorption of oxygen and/or water on the MoS2 surface with a positive or negative gate bias, respectively, under an ambient environment. This study will be helpful in understanding the electrical-stress-induced instability of the MoS2-based electronic devices and will also give insight into the design of desirable devices for electronics applications.