IBM has announced it has achieved a new data-transmission advancement that will help improve Internet backbone speeds to 200 — 400 gigabits per second (Gb/s) at extremely low power. The speed boost is based on a new lab prototype chip design that can be used to improve transfer of Big Data between clouds and data centers via fiber four times faster than current 100 Gb/s technology. A previous version of the technology has been licensed to Semtech Corp., a leading supplier of analog and mixed-signal semiconductors. Semtech is using that technology to develop advanced communications platforms expected to be announced later this year, ranging from optical and wireline communications to advanced radar systems.
As Big Data and Internet data traffic continue to grow exponentially, future networking standards have to support higher data rates. For example, in 1992, 100 gigabytes of data was transferred per day; today, traffic has grown to two exabytes per day, a 20-million-fold increase. To support the increase in traffic, scientists at IBM Research and Ecole Polytechnique Fédérale de Lausanne (EPFL) have been developing ultra-fast, energy-efficient, analog-to-digital converter (ADC) technology to enable transmission across long-distance fiber channels.
For example, scientists plan to use ADCs to convert the analog radio signals that originate from the cosmos to digital. It’s part of a collaboration called DOME between ASTRON, the Netherlands Institute for Radio Astronomy, DOME-South Africa, and IBM to develop a fundamental IT roadmap for the Square Kilometer Array (SKA), an international project to build the world’s largest and most sensitive radio telescope.
The analog radio data that the SKA collects from deep space is expected to produce multiple petabits (1015 bits) per second — 10 times the current global Internet traffic. IBM says the prototype ADC would be an ideal candidate to transport the signals fast and at very low power — a critical requirement considering the ~3,000 radio telescopes, each transmitting ~160 Gb/s, that will be spread over a square kilometer.
- Lukas Kull et al. A 90GS/s 8b 667mW 64× Interleaved SAR ADC in 32nm Digital SOI CMOS. International Solid-State Circuits Conference. Feb 12, 2014